WM8746

Production Data

w

March 2006, PD Rev 4.0

23

REGISTER MAP

The complete register map is shown below. The detailed description can be found in the relevant text of the device description.

There are 9 registers with 9 bits per register. These can be controlled using the Control Interface.

A6

A5

A4

A3

A2

A1

A0

D8

D7

D6

D5

D4

D3

D2

D1

D0

M0

0

0

0

0

0

0

0

UPDATE

L0A7

L0A 6

L0A 5

L0A 4

L0A 3

L0A 2

L0A 1

L0A 0

M1

0

0

0

0

0

0

1

UPDATE

R0A7

R0A 6

R0A 5

R0A 4

R0A 3

R0A 2

R0A 1

R0A 0

M2

0

0

0

0

0

1

0

PL3

PL2

PL1

PL0

IZD

ATC

PDWN

DEEMPH

MUTE

M3

0

0

0

0

0

1

1

REV2

REV1

REV0

IWL1

IWL0

BCP

LRP

FMT1

FMT0

M4

0

0

0

0

1

0

0

UPDATE

L1A7

L1A 6

L1A 5

L1A 4

L1A 3

L1A 2

L1A 1

L1A 0

M5

0

0

0

0

1

0

1

UPDATE

R1A7

R1A 6

R1A 5

R1A 4

R1A 3

R1A 2

R1A 1

R1A 0

M6

0

0

0

0

1

1

0

UPDATE

L2A7

L2A 6

L2A 5

L2A 4

L2A 3

L2A 2

L2A 1

L2A 0

M7

0

0

0

0

1

1

1

UPDATE

R2A7

R2A 6

R2A 5

R2A 4

R2A 3

R2A 2

R2A 1

R2A 0

M8

0

0

0

1

0

0

0

UPDATE MASTA7 MASTA 6 MASTA 5 MASTA 4 MASTA 3 MASTA 2 MASTA 1 MASTA 0

M9

0

0

0

1

0

0

1

0

0

0

0

0

0

0

ZCD

2SPD

Table 12 Register Map

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

L0A[7:0]

11111111

(0dB)

Attenuation level of left channel DACL0 in 0.5dB steps, see Table 8.

0000000

Attenuation

DACL0

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACL0 in intermediate latch (no change to output)

1: Store DACL0 and update attenuation on all channels.

7:0

R0A[7:0]

11111111

(0dB)

Attenuation level of left channel DACR0 in 0.5dB steps, see Table 8.

0000001

Attenuation

DACR0

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACR0 in intermediate latch (no change to output)

1: Store DACR0 and update attenuation on all channels.