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WM8746SEDS/R Datasheet(PDF) 25 Page - Wolfson Microelectronics plc |
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WM8746SEDS/R Datasheet(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 32 page ![]() WM8746 Production Data w March 2006, PD Rev 4.0 25 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 L1A[7:0] 11111111 (0dB) Attenuation level of left channel DACL1 in 0.5dB steps. See Table 8 0000100 Attenuation DACL1 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. 7:0 R1A[7:0] 11111111 (0dB) Attenuation level of right channel DACR1 in 0.5dB steps, see Table 8. 0000101 Attenuation DACR1 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. 7:0 L2A[7:0] 11111111 (0dB) Attenuation level of left channel DACL2 in 0.5dB steps, see Table 8. 0000110 Attenuation DACL2 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. 7:0 R2A[7:0] 11111111 (0dB) Attenuation level of right channel DACR2 in 0.5dB steps, see Table 8. 0000111 Attenuation DACR2 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. 7:0 MASTA[7:0] 11111111 (0dB) Attenuation data for all channels in 0.5dB steps, see Table 8. 0001000 Master Attenuation (all channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store DACR0 and update attenuation on all channels 0 2SPD 0 Activates the split rate mode where the front channels run at 192kHz and the rear four channels run at 96kHz. 0: Normal operation. 1: Split rate operation. 0001001 Extended interface control 1 ZCD 0 Controls the operation of the zero crossing detect mechanism which ensures that the volume is only updated on each channel when the signal passes through midrail. 0: Enable zero detect. 1: Disable zero detect. Table 13 Register Map Description |
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