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WM8746SEDS/R Datasheet(PDF) 24 Page - Wolfson Microelectronics plc |
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WM8746SEDS/R Datasheet(HTML) 24 Page - Wolfson Microelectronics plc |
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24 / 32 page ![]() WM8746 Production Data w March 2006, PD Rev 4.0 24 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 MUTE 0 Left and Right DACs soft mute control 0: No Mute 1: Mute 1 DEEMPH 0 De-emphasis Control 0: Normal Response (see Figure 14 - Figure 17) 1: De-emphasis Response (see Figure 18 - Figure 23) 2 PWDN 0 Left and Right DACs Power-down Control 0: All DACs running, output is active 1: All DACs in power saving mode, output muted 3 ATC 0 Attenuator Control 0: All DACs use attenuations as programmed. 1: Right chan. DACs use corresponding left DAC attenuations 4 IZD 0 Infinite zero detection circuit control and automute control 0: Infinite zero detect disabled 1: Infinite zero detect enabled DAC Output Control PL[3:0] Left Output Right Output PL[3:0] Left Output Right Output 0000 Mute Mute 1000 Mute Right 0001 Left Mute 1001 Left Right 0010 Right Mute 1010 Right Right 0011 (L+R)/2 Mute 1011 (L+R)/2 Right 0100 Mute Left 1100 Mute (L+R)/2 0101 Left Left 1101 Left (L+R)/2 0110 Right Left 1110 Right (L+R)/2 0000010 DAC Control 8:5 PL[3:0] 1001 0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2 1:0 FMT[1:0] 00 Interface format select 00: right justified mode 01: left justified mode 10: I 2S mode 11: DSP Mode A or B LRCIN Polarity or LRCIN Phase 2 LRP 0 Left Justified / Right Justified / I 2S 0: Standard LRCIN Polarity 1: Inverted LRCIN Polarity DSP Mode 0: DSP Mode A 1: DSP Mode B 3 BCP 0 BCKIN Polarity 0: Normal (DIN[2:0] and LRCIN sampled on rising edge) 1: Inverted (DIN[2:0] and LRCIN sampled on falling edge) 5:4 WL[1:0] 10 Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) 0000011 Interface Control 8:6 PHASE 000 Controls the output phase of the three stereo channels Bit 6 reverses the phase of data output on OUT0L/R. Bit 7 reverses the phase of data output on OUT1L/R. Bit 8 reverses the phase of data output on OUT2L/R. |
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