MSC7119 datasheet(25/56 Pages) FREESCALE

No. de pieza	MSC7119

Descripción Electrónicos	Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

PDF	56 Pages

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Fabricante Electrónico	FREESCALE [Freescale Semiconductor, Inc]

Página de inicio	http://www.freescale.com

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Electrical Characteristics

MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6

Freescale Semiconductor

2.5.3.2

Reset Configuration

The MSC7119 has two mechanisms for writing the reset configuration:

•

From a host through the host interface (HDI16)

•

From memory through the I2C interface

Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and

operating conditions:

•

BM[0–1]

•

SWTE

•H8BIT

•

HDSP

2.5.3.3

Reset Timing Tables

Table 16 and Figure 4 describe the reset timing for a reset configuration write.

Table 16. Timing for a Reset Configuration Write

No.

Characteristics

Expression

Unit

Required external PORESET duration minimum

16/FCLKIN

clocks

Delay from PORESET deassertion to HRESET deassertion

521/FCLKIN

clocks

Note:

Timings are not tested, but are guaranteed by design.

Figure 4. Timing Diagram for a Reset Configuration Write

PORESET

Internal

HRESET

Input

Output(I/O)

Configuration Pins

are sampled

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