MSC7119 datasheet(28/56 Pages) FREESCALE

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MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6

Electrical Characteristics

Freescale Semiconductor

Figure 7 provides the AC test load for the DDR DRAM bus.

2.5.5

TDM Timing

Figure 7. DDR DRAM AC Test Load

Table 19. DDR DRAM Measurement Conditions

Symbol

DDR DRAM

Unit

VTH

VREF ± 0.31 V

VOUT

0.5

× VDDM

Notes:

Data input threshold measurement point.

Data output measurement point.

Table 20. TDM Timing

No.

Characteristic

Expression

Min

Max

Units

300

TDMxRCK/TDMxTCK

20.0

—

301

TDMxRCK/TDMxTCK High Pulse Width

0.4

× TC

8.0

—

302

TDMxRCK/TDMxTCK Low Pulse Width

0.4

× TC

8.0

—

303

TDM all input Setup time

3.0

—

304

TDMxRD Hold time

3.5

—

305

TDMxTFS/TDMxRFS input Hold time

2.0

—

306

TDMxTCK High to TDMxTD output active

4.0

—

307

TDMxTCK High to TDMxTD output valid

—

14.0

308

TDMxTD hold time

2.0

—

309

TDMxTCK High to TDMxTD output high impedance

—

10.0

310

TDMxTFS/TDMxRFS output valid

—

13.5

311

TDMxTFS/TDMxRFS output hold time

2.5

—

Notes:

Output values are based on 30 pF capacitive load.

Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge

they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x

Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge.

Figure 8. TDM Receive Signals

Output

Z0 = 50 Ω

VOUT

RL = 50 Ω

TDMxRCK

TDMxRD

TDMxRFS

300

301

302

303

304

305

311

310

TDMxRFS (output)

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