MSC7119 datasheet(43/56 Pages) FREESCALE

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Hardware Design Considerations

MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6

Freescale Semiconductor

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Power planes. Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board power

supply. Each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct

groups of logic on the device. The MSC7119 VDDC power supply pins should be bypassed to ground using decoupling

capacitors. The capacitor leads and associated printed circuit traces connecting to device power pins and GND should

be kept to less than half an inch per capacitor lead. A minimum four-layer board that employs two inner layers as power

and GND planes is recommended. See Section 3.5 for DDR Controller power guidelines.

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Decoupling. Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use

standard capacitor values of 0.01

μF for every two to three voltage pins. For core voltage decoupling, use two levels

of decoupling. The first level should consist of a 0.01 µF high frequency capacitor with low effective series resistance

(ESR) and effective series inductance (ESL) for every two to three voltage pins. The second decoupling level should

consist of two bulk/tantalum decoupling capacitors, one 10

μF and one 47 μF, (with low ESR and ESL) mounted as

closely as possible to the MSC7119 voltage pins. Additionally, the maximum drop between the power supply and the

DSP device should be 15 mV at 1 A.

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PLL power supply filtering. The MSC7119 VDDPLL power signal provides power to the clock generation PLL. To

ensure stability of the internal clock, the power supplied to this pin should be filtered with capacitors that have low and

high frequency filtering characteristics. VDDPLL can be connected to VDDC through a 20 Ω resistor. VSSPLL can be tied

directly to the GND plane. A circuit similar to the one shown in Figure 31 is recommended. The PLL loop filter should

be placed as closely as possible to the VDDPLL pin (which are located on the outside edge of the silicon package) to

minimize noise coupled from nearby circuits.The 0.01 µF capacitor should be closest to VDDPLL, followed by the 0.1

µF capacitor, the 10 µF capacitor, and finally the 20-

Ω resistor to VDDC. These traces should be kept short.

Figure 30. Voltage Sequencing

Figure 31. PLL Power Supply Filter Circuits

Time

Differential should always be

0.7 V or more.

0.7 V or More

Ramp-down

Ramp-up

VDDIO = 3.3 V

VDDM = 2.5 V

VDDC = 1.2 V

VDDC

VDDPLL

0.1 µF 0.01 µF

10 µF

MSC7119 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

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