5.6 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0V to 5.5V, DVDD = 2.7V to 5.5V, VINP

= –1V to +1V, and SNSN = AGND; typical specifications are at TA = 25°C, AVDD = 5V, DVDD = 3.3V, and fCLKIN = 10MHz

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

CIN

Input capacitance

fCLKIN = 10MHz

2

pF

RIN

Input resistance

INP pin to AGND, SNSN = AGND

0.1

1

GΩ

IIB

Input bias current(1)

INP = AGND

–10

±3

10

nA

CMTI

Common-mode transient immunity

150

V/ns

DC ACCURACY

EO

Offset error

TA = 25°C, INP = AGND

–0.9

±0.08

0.9

mV

TCEO

Offset error temperature drift(3)

3.5

8.5

µV/°C

EG

Gain error(1)

Initial, at TA = 25°C,

VINP = 1V or VINP = –1V

–0.25

±0.02

0.25

%

TCEG

Gain error temperature drift(4)

–35

±10

35

ppm/°C

INL

Integral nonlinearity(2)

Resolution: 16 bits

–6

±1

6

LSB

DNL

Differential nonlinearity

Resolution: 16 bits

–0.99

0.99

LSB

PSRR

Power-supply rejection ratio

AVDD DC PSRR, IN = AGND,

AVDD from 3.0V to 5.5V

–83

dB

AVDD AC PSRR, IN = AGND,

AVDD with10kHz / 100mV ripple

–63

AC ACCURACY

SNR

Signal-to-noise ratio

VIN = 2VPP, fIN = 1kHz

86

89

dB

SINAD

Signal-to-noise + distortion

VIN = 2VPP, fIN = 1kHz

77

88

dB

THD

Total harmonic distortion(5)

VIN = 2VPP, fIN = 1kHz

–91

–80

dB

DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)

IIN

Input current

DGND ≤ VIN ≤ DVDD

7

µA

CIN

Input capacitance

4

pF

VIH

High-level input voltage

0.7 x DVDD

DVDD + 0.3

V

VIL

Low-level input voltage

–0.3

0.3 x DVDD

V

DIGITAL OUTPUT (CMOS)

CLOAD

Output load capacitance

fCLKIN = 10MHz

15

30

pF

VOH

High-level output voltage

IOH = –4mA

DVDD – 0.4

V

VOL

Low-level output voltage

IOL = 4mA

0.4

V

POWER SUPPLY

IAVDD

High-side supply current

5.3

7

mA

IDVDD

Low-side supply current

CLOAD = 15pF

3.6

5

mA

AVDDUV

High-side undervoltage detection

threshold

AVDD rising

2.4

2.6

2.7

V

AVDD falling

1.9

2.0

2.1

DVDDUV

Low-side undervoltage detection

threshold

DVDD rising

2.3

2.5

2.7

V

DVDD falling

1.9

2.0

2.1

(1)

The typical value includes one sigma statistical variation.

(2)

Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(3)

Offset error drift is calculated using the box method, as described by the following equation:

TCEO = (valueMAX - valueMIN) / TempRange

(4)

Gain error drift is calculated using the box method, as described by the following equation:

TCEG (ppm) = ((valueMAX - valueMIN) / (value x TempRange)) X 106

(5)

THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.

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AMC0136

SBASAZ0A – AUGUST 2024 – REVISED DECEMBER 2024

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