6.3.4 Digital Output

An input signal of 0V ideally produces a stream of ones and zeros that are high 50% of the time. An input of 1V

produces a stream of ones and zeros that are high 90.0% of the time. With 16 bits of resolution, that percentage

ideally corresponds to code 58982. An input of –1V produces a stream of ones and zeros that are high 10.0%

of the time. With 16 bits of resolution, that percentage ideally corresponds to code 6554. These input voltages

are also the specified linear range of the AMC0136. If the input voltage value exceeds this range, the output of

the modulator shows increasing nonlinear behavior as the quantization noise increases. The modulator output

clips with a constant stream of zeros at an input ≤–1.25V or with a constant stream of ones at an input ≥1.25V.

In this case, however, the AMC0136 generates a single 1 or 0 every 128 clock cycles to indicate proper device

function. A single 1 is generated if the input is at negative fullscale and a 0 is generated if the input is at positive

fullscale. See the Output Behavior in Case of a Full-Scale Input section for more details. Figure 6-4 shows the

input voltage versus the output modulator signal.

Modulator Output

+ FS (Analog Input)

– FS (Analog Input)

Analog Input

Figure 6-4. Modulator Output vs Analog Input

Calculate the density of ones in the output bitstream with Equation 1 for any input voltage VIN = (V INP – V SNSN )

value. The only exception is a fullscale input signal. See the Output Behavior in Case of a Full-Scale Input

section.

⍴ = (|VClipping| + VIN) / (2 x VClipping)

(1)

6.3.4.1 Output Behavior in Case of a Full-Scale Input

If a fullscale input signal is applied to the AMC0136, the device generates a single one or zero every 128 bits

at DOUT. Figure 6-5 shows a timing diagram of this process. A single 1 or 0 is generated depending on the

actual polarity of the signal being sensed. A fullscale signal is defined as |V INP – V SNSN | ≥ |VClipping|. In this

way, differentiating between a missing AVDD and a fullscale input signal is possible on the system level. See the

Diagnosing Delta-Sigma Modulator Bitstream Using C2000™ Configurable Logic Block (CLB) application note

for code examples of diagnosing the digital bitstream.

DOUT

CLKIN

127 CLKIN cycles

127 CLKIN cycles

VIN

VFSR, MIN

VIN

VFSR, MAX

DOUT

Figure 6-5. Fullscale Output of the AMC0136

AMC0136

SBASAZ0A – AUGUST 2024 – REVISED DECEMBER 2024

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