Connection Diagram

Function Table

Latch Selection Table

H

= HIGH Level

L

= LOW Level

D

= the Level of the Data Input

Qi0 = the Level of Qi (i = 0, 1,…7, as Appropriate) before the Indicated

Steady-State Input Conditions Were Established.

Inputs

Output of

Each

Addressed

Other

Function

Clear

E

Latch

Output

HL

D

Qi0

Addressable Latch

HH

Qi0

Qi0

Memory

L

L

D

L

8-Line Demultiplexer

L

H

L

L

Clear

Select Inputs

Latch

C

B

A

Addressed

LLL

0

LL

H

1

LH

L

2

LH

H

3

HL

L

4

HL

H

5

HH

L

6

HHH

7

www.sycelectronica.com.ar