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STM32H523VCU6 Datasheet(PDF) 187 Page - STMicroelectronics

No. de pieza STM32H523VCU6
Descripción Electrónicos  Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS
PDF  228 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H523VCU6 Datasheet(HTML) 187 Page - STMicroelectronics

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DS14540 Rev 1
187/228
STM32H523xx
Electrical characteristics
197
•
VOS level set to VOS0
Refer to Section 5.3.14 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).
Table 109. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tSCK
SPI clock frequency
Master receiver mode
2.7 V < VDD < 3.6 V
-
-
135/3(2)
MHz
Master receiver mode
1.71 V < VDD < 2.7 V
-
-
120/3(2)
Master transmitter mode
2.7 V < VDD < 3.6 V
135/3(2)
Master transmitter mode
1.71 V < VDD < 2.7 V
-
-
120/3(2)
Slave receiver mode
1.71 V < VDD < 3.6 V
--
120
Slave transmitter mode
2.7 V < VDD < 3.6 V
--
43(3)/6(4)
Slave transmitter mode
1.71 V < VDD < 2.7 V
--
41.5(3)/6(4)
tsu(NSS)
NSS setup time
Slave mode
3.5
-
-
ns
th(NSS)
NSS hold time
Slave mode
4.5
-
-
ns
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
tSCK(5) - 1
tSCK(5)
tSCK(5) + 1
ns
tsu(MI)
Data input setup time
Master mode
3.5
-
-
ns
tsu(SI)
Slave mode
2
-
-
th(MI)
Data input hold time
Master mode
1
-
-
ns
th(SI)
Slave mode
1.5
-
-
ta(SO)
Data output access time
Slave mode
6.5
13
15
ns
tdis(SO)
Data output disable time
Slave mode
7.5
13
18
ns
tv(SO)
Data output valid time
Slave mode
(after enable edge),
2.7 V < VDD < 3.6 V
-
10/26.5(4) 11.5/35.5(4)
ns
Slave mode
(after enable edge),
1.71 V < VDD < 2.7 V
-11/61.5(4)
12/76(4)
tv(MO)
Master mode
(after enable edge)
-1.5
2
th(SO)
Data output hold time
Slave mode
(after enable edge)
6.5/20.5(4)
--
ns
th(MO)
Master mode
(after enable edge)
0-
-
1. Evaluated by characterization - Not tested in production.



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