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STM32H523VCU6 Datasheet(PDF) 188 Page - STMicroelectronics

No. de pieza STM32H523VCU6
Descripción Electrónicos  Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS
PDF  228 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H523VCU6 Datasheet(HTML) 188 Page - STMicroelectronics

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Electrical characteristics
STM32H523xx
188/228
DS14540 Rev 1
Figure 49. SPI timing diagram - Master mode
1. The SS input can be configured to active low or active high.
Figure 50. SPI timing diagram - Slave mode and CPHA = 0
2. When using PB13.
3. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which must fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
4. When using PB14.
5. tSCK = tker_ck * Baud rate prescaler.
MSv69586V2
th(MI)
tc(SCK)
tw(SCKH)
tw(SCKL)
SS input
(1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MOSI output
MISO input
First bit OUT
Last bit OUT
Next bits OUT
First bit IN
Last bit IN
Next bits IN
CPHA=1
CPOL=0
CPHA=1
CPOL=1
High
tv(MO)
th(MO)
tsu(MI)
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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