STM32H523VCY7 datasheet(25/228 Pages) STMICROELECTRONICS

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DS14540 Rev 1

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STM32H523xx

Functional overview

3.9

TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTSR2 register.

When the TrustZone is enabled, the SAU (security attribution unit) and IDAU

(implementation defined attribution unit) define the access permissions based on secure

and non-secure state.

•

SAU: up to eight SAU configurable regions are available for security attribution.

•

IDAU: It provides a first memory partition as non-secure or non-secure callable

attributes. It is then combined with the results from the SAU security attribution and the

higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs and peripherals

memory space is aliased twice for secure and non-secure states. However, the external

memories space is not aliased.

3.9.1

TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-

aware type as follows:

•

securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to

define security properties

•

TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing

a specific TrustZone behavior such as a subset of registers being secure

3.9.2

Default TrustZone security state

The default system security state is detailed below:

•

CPU:

–

Cortex-M33 is in secure state after reset. The boot address must be in secure

address.

•

Memory map:

–

SAU is fully secure after reset. Consequently, all memory map is fully secure. Up

to eight SAU configurable regions are available for security attribution.

•

Flash memory:

–

Flash memory security area is defined by watermark user options.

–

Flash memory block based area is non-secure after reset.

•

SRAMs:

–

All SRAMs are secure after reset. MPCBB (memory protection block based

controller) is secure.

•

External memories:

–

FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection

watermark based controller) is secure.

•

Peripherals

–

Securable peripherals are non-secure after reset.

–

TrustZone-aware peripherals are non-secure after reset. Their secure

configuration registers are secure.

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