CDCE62005RGZR datasheet(3/76 Pages) TI

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PACKAGE

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CDCE62005

www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008

The CDCE62005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for

heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48)

Figure 2. 48-Pin QFN Package Outline

PIN FUNCTIONS

TYPE

DESCRIPTION

NAME

QFN

VCC_OUT

8, 11,

Power

3.3V Supply for the Output Buffers

18, 21,

26, 29,

VCC_AUXOUT

Power

3.3V to Power the AUX_OUT circuitry

VCC1_PLL

A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required)

VCC2_PLL

39, 42

A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required)

VCC_VCO

34, 35

A. Power 3.3V VCO Input Buffer and Circuitry Supply Voltage. (Filter Required)

VCC_IN_PRI

A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.

VCC_IN_SEC

A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.

VCC_AUXIN

A. Power 3.3V Crystal Oscillator Input Circuitry.

GND_VCO

Ground

Ground that connects to VCO Ground. (VCO_GND is shorted to GND)

GND

PAD

Ground

Ground is on Thermal PAD. See Layout recommendation

SPI_MISO

In SPI Mode it is an Open Drain Output and it functions as a Master In Slave Out as a serial

Control Data Output to CDCE62005 .

SPI_LE

LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in

SPI Mode. The input has an internal 150-k

Ω pull-up resistor if left unconnected it will default to

logic level “1”.

SPI_CLK

LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has

an internal 150-k

Ω pull-up resistor if left unconnected it will default to logic level “1”.

SPI_MOSI

LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the SPI bus

interface. The input has an internal 150-k

Ω pull-up resistor if left unconnected it will default to logic

level “1”.

TEST_MODE

This pin should be tied high or left unconnected.

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