CDCE62005RGZR datasheet(2/76 Pages) TI

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DESCRIPTION

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Data

DSP

CDCE62005

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DSP Clock

ADCClock

DACClock

DEVICE INFORMATION

CDCE62005

SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree

of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM.

Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter

performance well under 1 ps RMS(1). It incorporates a synthesizer block with partially integrated loop filter, a

clock distribution block including programmable output formats, and an input block featuring an innovative smart

multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to

provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be

programmed to a unique output frequency (ranging from 800 kHz to 1.5 GHz (2)) and skew relationship via a

programmable delay block. If all outputs are configured in single-ended mode (e.g., LVCMOS), the CDCE62005

supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including

any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal

differential inputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be

connected to a CMOS level clock or configured to connect to an external crystal via an on board oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user

selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically

select between the highest priority input clock available.

Figure 1. CDCE62005 Application Example

(1)

10 kHz to 20 MHz integration bandwidth.

(2)

Frequency range depends on operational mode and output format selected.

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