CDCE62005RGZR datasheet(68/76 Pages) TI

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APPLICATION INFORMATION AND GENERAL USAGE HINTS

/1 - /80

U0P

U0N

PRI_IN

SEC _IN

/1 - /80

U4P

U4N

Divide by 1: Upto 1500 MHz

Otherwise : Upto 1175 MHz

Upto 5 Outputs :

LVPECL orLVDS

Upto 10 Outputs:

LVCMOS

XTAL /

AUX _IN

Output

Divider 0

U0P

U0N

PFD/

Prescaler

Feedback

Divider

Input

Divider

Smart

MUX

Output

Divider 4

U4P

U4N

CDCE62005

SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com

Fan-out Buffer

Each output of the CDCE62005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with

divide and skew control functionality.

Figure 41. CDCE62005 Fan-out Buffer Mode

Clock Generator

The CDCE62005 can generate 5–10 low noise clocks from a single crystal or crystal oscillator as follows:

Figure 42. CDCE62005 Clock Generator Mode

Jitter Cleaner – Mixed Mode (1)

The following table presents a common scenario. The CDCE62005 must generate several integer-related clocks

from a reference that has traversed a backplane. In order for jitter cleaning to take place, the phase noise of the

on-board clock path must be better than that of the incoming clock. The designer must pay attention to the

optimization of the loop bandwidth of the synthesizer and understand the phase noise profiles of the oscillators

involved. Further, other devices on the card require clocks at frequencies not related to the backplane clock. The

system requires combinations of differential and single-ended clocks in specific formats with specific phase

relationships. (1)

CLOCK FREQUENCY

INPUT/OUTPUT

FORMAT

NUMBER

CDCE62005 PORT

COMMENT

10.000 MHz

Input

LVDS

SEC_IN

Low end crystal oscillator

30.72 MHz

Input

LVDS

PRI_IN

Reference from backplane

122.88 MHz

Output

LVDS

SERDES Clock

491.52 MHz

Output

LVPECL

ASIC

245.76 MHz

Output

LVPECL

FPGA

30.72 MHz

Outputs

LVCMOS

ASIC

10.000 MHz

Outputs

LVCMOS

CPU, DSP

(1)

Pay special attention when using the universal inputs with two different clock sources. Two clocks derived from the same source may

use the internal bias generator and internal termination network without jitter performance degradation. However, if their origin is from

different sources (e.g. two independent oscillators) then sharing the internal bias generator can degrade jitter performance significantly.

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CDCE62005RGZR Datasheet(PDF) 68 Page - Texas Instruments

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