HC230 datasheet(25/228 Pages) ALTERA

25 / 228 page

Altera Corporation

2–17

September 2008

Preliminary

I/O Structure and Features

The three types of IOEs are located in different areas of the device and are

described in the following sections. HardCopy II devices have eight I/O

banks, just as in Stratix II FPGAs. Figures 2–4 through 2–6 show which

I/O type each bank supports.

LVPECL

Differential

3.3/2.5/

1.8/1.5

(8)

Notes to Table 2–9:

(1)

Pseudo-differential HSTL and SSTL inputs only use the positive-polarity input in the speed path. The negative

input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with

the second output programmed as inverted. This is similar to a Stratix II device implementation.

(2)

The PCI clamping diode is only supported on the I/O pins on the top and bottom sides of the device.

(3)

This I/O standard is only supported on the DQS,

CLK and PLL_FB input pins or on the PLL_OUT output pins.

(4)

This I/O standard is only supported on the bottom

CLK and PLL_FB input pins or on the bottom PLL_OUT output

pins.

(5)

This I/O standard is only supported on the

CLK and PLL_FB input pins or on the PLL_OUT output pins.

(6)

Also supported on

CLK9 and CLK11 pins.

(7)

This I/O standard is only supported on

CLK and PLL_FB input pins.

(8)

LVPECL input I/O standard is supported on the top and bottom

CLK and PLL_FB input pins. LVPECL output I/O

standard is supported on the top and bottom

PLL_OUT output pins. LVPECL support is similar to Stratix II devices.

Table 2–9. HardCopy II Supported I/O Standards (Part 3 of 3)

I/O Standard

Type

VCCIO Level (V)

Memory

Interface

IOEs

General

Purpose IOEs

High-Speed

IOEs

Input

Output

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