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MPC8377ECVRALDA Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc |
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MPC8377ECVRALDA Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 124 page ![]() MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 29 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 8.2.3.2 RMII Receive AC Timing Specifications Table 29 shows the RMII receive AC timing specifications. Figure 13 provides the AC test load for eTSEC. Figure 13. eTSEC AC Test Load Table 29. RMII Receive AC Timing Specifications At recommended operating conditions with LVDD of 3.3 V ± 5%. Parameter/Condition Symbol1 Min Typical Max Unit Input low voltage at 3.3 LVDD VIL —— 0.8 V Input high voltage at 3.3 LVDD VIH 2.0 — — V REF_CLK clock period tRMR 15.0 20.0 25.0 ns REF_CLK duty cycle tRMRH 35 50 65 % REF_CLK peak-to-peak jitter tRMRJ — — 250 ps Rise time REF_CLK (20%–80%) tRMRR 1.0 — 2.0 ns Fall time REF_CLK (80%–20%) tRMRF 1.0 — 2.0 ns RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge tRMRDV 4.0 — — ns RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge tRMRDX 2.0 — — ns Note: 1 The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Output Z0 = 50 Ω LVDD/2 RL = 50 Ω |
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