MPC8377ECVRALDA datasheet(42/124 Pages) FREESCALE

No. de pieza	MPC8377ECVRALDA

Descripción Electrónicos	PowerQUICC??II Pro Processor Hardware Specifications

PDF	124 Pages

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Fabricante Electrónico	FREESCALE [Freescale Semiconductor, Inc]

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)

11 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the

MPC8377E.

The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the

SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full-

and high-speed modes.

Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed

mode, that data will be driven at the rising edge of the clock.

LCLK

UPM Mode Input Signal:

LUPWAIT

tLBIXKH

tLBIVKH

tLBIXKH

GPCM Mode Output Signals:

LCS[0:7]/LWE[0:3]

tLBKHOV

tLBKHOZ

Input Signals:

LAD[0:31]

UPM Mode Output Signals:

LCS[0:7]/LBS[0:1]/LGPL[0:5]

tLBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

tLBKHOZ

tLBKHOV

MPC8377ECVRALDA Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc