MPC8377ECVRALDA datasheet(63/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI Express

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always

relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx

UI.

NOTE

It is recommended that the recovered Tx UI be calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

Figure 42. Minimum Transmitter Timing and Voltage Output Compliance Specifications

15.4.3

Differential Receiver (Rx) Input Specifications

Table 52 defines the specifications for the differential input at all receivers. The parameters are specified

at the component pins.

Table 52. Differential Receiver (Rx) Input Specifications

Parameter

Comments

Symbol

Min

Typical

Max

Units

Notes

Unit interval

Each UPERX is 400 ps ± 300

ppm. UPERX does not account

for Spread Spectrum Clock

dictated variations.

399.88

400

400.12

Differential peak-to-peak

output voltage

VPEDPPRX = 2 × |VRX-D+ –

VRX-D-|

VRX-DIFFp-p

0.175

—

1.200

[De-emphasized Bit]

566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

MPC8377ECVRALDA Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc

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