MPC5634MF0MLQA4 datasheet(25/118 Pages) FREESCALE

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Overview

MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

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5 independent timer channels

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Each channel includes 32-bit wide down counter with automatic reload

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4 channels clocked from system clock

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1 channel clocked from crystal clock (wake-up timer)

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Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined

time-out period

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Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer

reaches zero

1.3.18.2

System Timer Module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see

http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer

comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:

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One 32-bit up counter with 8-bit prescaler

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Four 32-bit compare channels

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Independent interrupt source for each channel

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Counter can be stopped in debug mode

1.3.19

Software Watchdog Timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog

integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can

provide a system reset or interrupt request when the correct software key is not written within the required time window.

The following features are implemented:

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32-bit modulus counter

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Clocked by system clock or crystal clock

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Optional programmable watchdog window mode

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Can optionally cause system reset or interrupt request on timeout

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Reset by writing a software key to memory mapped register

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Enabled out of reset

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Configuration is protected by a software key or a write-once register

1.3.20

Nexus Port Controller

The NPC (Nexus Port Controller) block provides real-time development support capabilities for the MPC5634M Power

Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for

MCUs without requiring external address and data pins for internal visibility. The NPC block is an integration of several

individual Nexus blocks that are selected to provide the development support interface for the MPC5634M. The NPC block

interfaces to the host processor (e200z335), eTPU, and internal buses to provide development support as per the IEEE-ISTO

5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal

memory map and access to the Power Architecture and eTPU internal registers during halt. The Nexus interface also supports

a JTAG only mode using only the JTAG pins. MPC5634M in the production 144 LQFP supports a 3.3 V reduced (4-bit wide)

Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable I/O count of the device. When using

this Nexus port as IO, Nexus trace is still possible using VertiCal calibration. In the VertiCal calibration package, the full 12-bit

Auxiliary port is available.

MPC5634MF0MLQA4 Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc

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