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MPC5634MF0MLQA4 Datasheet(PDF) 1 Page - Freescale Semiconductor, Inc |
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MPC5634MF0MLQA4 Datasheet(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 118 page  Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5634M Rev. 4, 12/2009 © Freescale Semiconductor, Inc., 2008, 2009. All rights reserved. Preliminary—Subject to Change Without Notice This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MPC5634M 208 MAPBGA 17 mm x 17 mm 144 LQFP 20 mm x 20 mm 176 LQFP 24 mm x 24 mm • Operating Parameters – Fully static operation, 0 MHz - 80 MHz (plus 2% frequency modulation - 82 MHz) –-40 °C to 150 °C junction temperature operating range – Low power design – Less than 400 mW power dissipation (nominal) – Designed for dynamic power management of core and peripherals – Software controlled clock gating of peripherals – Low power stop mode, with all clocks stopped – Fabricated in 90 nm process – 1.2 V internal logic • High performance e200z335 core processor • Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR) • Enhanced direct memory access (eDMA) controller • Interrupt controller (INTC) – 191 peripheral interrupt request sources, plus 165 reserved positions – Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor • Frequency Modulating Phase-locked loop (FMPLL) • Calibration bus interface (EBI) (available only in the calibration package) • System integration unit (SIU) centralizes control of pads, GPIO pins and external interrupts. • Error correction status module (ECSM) provides configurable error-correcting codes (ECC) reporting • Up to 1.5 MB on-chip flash memory • Up to 94 KB on-chip static RAM • Boot assist module (BAM) enables and manages the transition of MCU from reset to user code execution from internal flash memory, external memory on the calibration bus or download and execution of code via FlexCAN or eSCI. • Periodic interrupt timer (PIT) – 32-bit wide down counter with automatic reload – 4 channels clocked by system clock – 1 channel clocked by crystal clock • System timer module (STM) – 32-bit up counter with 8-bit prescaler – Clocked from system clock – 4 channel timer compare hardware • Software watchdog timer (SWT) 32-bit timer • Enhanced modular I/O system (eMIOS) – 16 standard timer channels (up to 14 channels connected to pins in LQFP144) – 24-bit timer resolution • Second-generation enhanced time processor unit (eTPU2) – High level assembler/compiler – Enhancements to make ‘C’ compiler more efficient – New ‘engine relative’ addressing mode • Enhanced queued A/D converter (eQADC) – 2 independent on-chip RSD Cyclic ADCs – Up to 34 input channels available to the two on-chip ADCs – 4 pairs of differential analog input channels • 2 deserial serial peripheral interface modules (DSPI) – SPI provides full duplex communication ports with interrupt and DMA request support – Deserial serial interface (DSI) achieves pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO • 2 enhanced serial communication interface (eSCI) modules • 2 FlexCAN modules • Nexus port controller (NPC) per IEEE-ISTO 5001-2003 standard • IEEE 1149.1 JTAG controller (JTAGC) MPC5634M Microcontroller Data Sheet |
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