MPC5634MF0MLQA4 datasheet(15/118 Pages) FREESCALE

15 / 118 page

Overview

MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1.3.6

Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal

connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System. The

Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The

Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI

supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed

region-specific attributes. The calibration EBI supports the following features:

•

22-bit address bus (two most significant signals multiplexed with two chip selects)

•

16-bit data bus

•

Multiplexed mode with addresses and data signals present on the data lines

NOTE

The calibration EBI must be configured in multiplexed mode when the extended Nexus

trace is used on the VertiCal Calibration System. This is because Nexus signals and address

lines of the calibration bus share the same balls in the calibration package.

•

Memory controller with support for various memory types:

— Asynchronous/legacy flash and SRAM

— Most standard memories used with the MPC5xx or MPC55xx family

•

Bus monitor

— User selectable

— Programmable time-out period (with 8 external bus clock resolution)

•

Configurable wait states (via chip selects)

•

3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals)

•

2 write/byte enable (WE[0:1]/BE[0:1]) signals

•

Configurable bus speed modes

— system frequency

— 1/2 of system frequency

— 1/4 of system frequency

•

Optional automatic CLKOUT gating to save power and reduce EMI

•

Compatible with MPC5xx external bus (with some limitations)

•

Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

1.3.7

SIU

The MPC5634M SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),

internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot

configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block

provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring

of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU

core is via the crossbar switch. The SIU provides the following features:

•

System configuration

— MCU reset configuration via external pins

— Pad configuration control for each pad

— Pad configuration control for virtual I/O via DSPI serialization

•

System reset monitoring and generation

— Power-on reset support

— Reset status register provides last reset source to software

MPC5634MF0MLQA4 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

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