MPC8378E datasheet(29/127 Pages) FREESCALE

29 / 127 page

MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

8.3.1.2

SGMII Receive AC Timing Specifications

Table 29 provides the SGMII receive AC timing specifications. Source synchronous clocking is not

supported; the clock is recovered from the data.

Figure 10 shows the SGMII receiver input compliance mask eye diagram.

Figure 10. SGMII Receiver Input Compliance Mask

Table 29. SGMII Receive AC Timing Specifications

At recommended operating conditions with XVDD_SRDS = 1.0 V ± 5%.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Deterministic jitter tolerance

0.37

—

UIp-p

Combined deterministic and random jitter tolerance

JDR

0.55

—

UIp-p

Sinusoidal jitter tolerance

JSIN

0.1

—

UIp-p

Total jitter tolerance

0.65

—

UIp-p

Bit error ratio

BER

—

10-12

——

Unit interval

799.92

800

800.08

AC-coupling capacitor

CTX

5—

200

Note:

1 Measured at the receiver.

2 Each UI is 800 ps ± 100 ppm.

3 The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs.

0.275

0.4

0.6

0.725

VRX_DIFFp-p-max/2

VRX_DIFFp-p-min/2

–VRX_DIFFp-p-min/2

–VRX_DIFFp-p-max/2

Time (UI)

MPC8378E Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

MPC8378E Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL