MPC8378E datasheet(33/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 14 provides the AC test load for eTSEC.

Figure 14. eTSEC AC Test Load

Duty cycle for 1000Base-T

tRGTH/tRGT

Duty cycle for 10BASE-T and 100BASE-TX

tRGTH/tRGT

3, 4

Rise time (20%–80%)

tRGTR

—

0.75

—

Fall time (20%–80%)

tRGTF

—

0.75

—

EC_GTX_CLK125 reference clock period

tG12

—8.0

—

EC_GTX_CLK125 reference clock duty cycle

measured at 0.5

× LV

DD1

tG125H/tG125

—

Note:

1 Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being

represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2 This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3 For 10 and 100 Mbps, t

RGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between

5 This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.

Table 33. RGMII and RTBI AC Timing Specifications (continued)

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

Notes

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

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