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MPC8378E Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

No. de pieza MPC8378E
Descripción Electrónicos  PowerQUICC II Pro Processor Hardware Specifications
PDF  127 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8378E Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
15
RESET Initialization
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8378E.
5.1
RESET DC Electrical Characteristics
Table 10 provides the DC electrical characteristics for the RESET pins of the device.
5.2
RESET AC Electrical Characteristics
Table 11 provides the reset initialization AC timing specifications of the device.
Table 10. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
OVDD + 0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
——
± 30
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Note:
• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
• HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET to activate reset flow
32
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
32
tCLKIN
2
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
tPCI_SYNC_IN
1
HRESET assertion (output)
512
tPCI_SYNC_IN
1
HRESET negation to negation (output)
16
tPCI_SYNC_IN
1
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
4—
tCLKIN
2
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR config signals with respect to negation of HRESET
0—
ns



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