MPC8378E datasheet(89/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 63. Differential Measurement Points for Rise and Fall Time

Figure 64. Single-Ended Measurement Points for Rise and Fall Time Matching

Rising edge rate (SDn_REF_CLK) to falling edge rate

(SDn_REF_CLK) matching

Rise-Fall Matching

—

1, 4

Note:

1 Measurement taken from single ended waveform.

2 Measurement taken from differential waveform.

3 Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is

centered on the differential zero crossing. See Figure 63.

4 Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a

200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median

cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge

Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference

should not exceed 20% of the slowest edge rate. See Figure 64.

Table 67. SerDes Reference Clock Common AC Parameters (continued)

At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

VIH = +200 mV

0.0 V

VIL = –200 mV

SDn_REF_CLK

Minus

SDn_REF_CLK

Rise Edge Rate

Fall Edge Rate

TFALL TRISE

SDn_REF_CLK

VCROSS MEDIAN

SDn_REF_CLK

VCROSS MEDIAN

SDn_REF_CLK

VCROSS MEDIAN –100 mV

VCROSS MEDIAN +100 mV

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