AD7280ABSTZ datasheet(16/48 Pages) AD

16 / 48 page

AD7280A

Rev. 0 | Page 16 of 48

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

VIN0

ADC VIN+

ADC VIN–

Figure 23. Mux Configuration During VIN2 to VIN1 Sampling

The ADC is a successive approximation register analog-to-

digital converter (SAR ADC). The converter is composed of

a comparator, a SAR, control logic, and two capacitive DACs.

Figure 24 shows a simplified schematic of the converter. During

the acquisition phase, the SW1, SW2, and SW3 switches are

closed. The sampling capacitor array acquires the signal on the

input during this phase.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

VIN+

VIN–

Figure 24. ADC Configuration During Acquisition Phase

When the ADC starts a conversion, SW3 opens, and SW1 and

SW2 move to Position B, causing the comparator to become

unbalanced (see Figure 25). The control logic and capacitive DACs

are used to add and subtract fixed amounts of charge to return

the comparator to a balanced condition. When the comparator

is rebalanced, the conversion is complete. The control logic gen-

erates the ADC output code. This output code is then stored in

the appropriate register for the input that has been converted.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

VIN+

VIN–

VREF

Figure 25. ADC Configuration During Conversion Phase

ANALOG INPUT STRUCTURE

Figure 26 shows the equivalent circuit of the analog input

structure of the AD7280A. The diodes provide ESD protection.

The resistors are lumped components made up of the on

resistance of the input multiplexer, internal track resistance,

and other internal switches. The value of these resistors is

approximately 300 Ω typical. Capacitor C1 is also a lumped

component made up of pin capacitance, ESD diodes, and switch

capacitance, whereas Capacitor C2 is the sampling capacitor

of the ADC. The total lumped capacitance of C1 and C2 is

approximately 15 pF.

VDD

VIN+

VSS

VDD

VIN–

VSS

Figure 26. Equivalent Analog Input Circuit

TRANSFER FUNCTION

The output coding of the AD7280A is straight binary. The designed

code transitions occur at successive integer LSB values (that is,

1 LSB, 2 LSBs, and so on). The LSB size is dependent on whether

the cell voltage or the auxiliary ADC inputs are being measured.

The analog input range of the voltage inputs is 1 V to 5 V, and

the analog input range of the auxiliary ADC inputs is 0 V to 5 V.

The ideal transfer characteristic is shown in Figure 27.

Table 7. LSB Sizes for Each Analog Input Range

Selected Inputs

Input

Range

Full-Scale

Range

LSB Size

Cell Voltage

1 V to 5 V

4 V/4096

976 μV

Auxiliary ADC Inputs

0 V to 5 V

5 V/4096

1.22 mV

111...110

111...000

011...111

000...010

000...001

000...000

111...111

ANALOG INPUT

1V + 1LSB

AGND + 1LSB

5V – 1LSB

4V INPUT RANGE

5V INPUT RANGE

Figure 27. Ideal Transfer Characteristic

AD7280ABSTZ Datasheet(PDF) 16 Page - Analog Devices

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