AD7280ABSTZ datasheet(29/48 Pages) AD

29 / 48 page

AD7280A

Rev. 0 | Page 29 of 48

Select Conversion Inputs

Bits[D15:D14] of the control register determine which cell

voltages and auxiliary ADC inputs are converted following a

convert start command. The default value of D15 and D14 on

power-up is 00.

Read Conversion Results

Bits[D13:D12] of the control register determine which cell

voltage and auxiliary ADC conversion results are supplied to

the serial or daisy-chain data output pins for readback. The

default value of D13 and D12 on power-up is 00.

Conversion Start Format

A conversion on the AD7280A can be initiated through the

hardware CNVST pin or by issuing a software convert start

command. Bit D11 of the control register determines whether a

conversion is initiated on the falling edge of the CNVST input

or on the rising edge of the CS input. The default format on

power-up is the CNVST pin, that is, 0. When using the rising

edge of the CS input to initiate conversions, Bit D11 is reset to

0 following the initiation of conversions.

Conversion Averaging

Bits[D10:D9] of the control register determine the number of

conversions completed on each input with the averaged results

stored in the relevant result registers. The user can select a single

conversion only or the average of two, four, or eight conversions.

The default value of Bits[D10:D9] on power-up is 00, that is,

single conversion only.

Power-Down Format

Setting Bit D8 of the control register places the AD7280A into

software power-down. See the Power-Down section for more

information. The default value of Bit D8 on power-up is 0.

Software Reset

Bit D7 of the control register allows the user to initiate a software

reset of the AD7280A. Two write commands are required to

complete the reset operation. Bit D7 must be set high to put the

AD7280A into reset. Bit D7 must then be set low to take the

AD7280A out of reset. A software reset resets all user configurable

registers to their default values with the exception of the lower

byte of the control register (Address 0x0E). When executing a

software reset, care should be taken to ensure that Bits[D6:D0]

are not incorrectly overwritten.

Set Acquisition Time

Bits[D6:D5] of the control register determine the acquisition

time of the ADC. See the Acquisition Time section for more

information. The default value of the acquisition time is 400 ns,

that is, 00.

Thermistor Termination Resistor

Bit D3 of the control register should be set if the user wishes to

use a single thermistor termination resistor on the AUXTERM pin.

Note that, due to settling time requirements, the thermistor

termination resistor option should only be used when the acqui-

sition time of the AD7280A is set to its highest value, that is,

1.6 μs (set Bits[D6:D5] to 11). The default value of D3 is 0.

Lock Device Address

Bit D2 of the control register is used in conjunction with Bit D1

to allow individual device addresses for each AD7280A in the

daisy chain to be defined and locked to the part. Bit D1 is used

to generate the individual device addresses that are presented to

each AD7280A in the daisy chain in the form of a write command.

When Bit D2 is set high, the AD7280A locks to the device address

presented to it. This new device address is used for all subsequent

CRC calculations. When Bit D2 is set low, the device address of

the AD7280A is not locked. In this case, a device address of 0x00

is used for CRC calculations. The default value of D2 is 0.

Increment Device Address

Bit D1 of the control register determines whether the AD7280A

increments the device address that it receives as part of a write

command when transferring that command up the daisy chain.

When Bit D1 is set to 1, the device address is incremented as the

command is passed up the chain. This mode of operation is used

on initial power-up and when coming out of a hardware power-

down to allow individual device addresses for each AD7280A in

the daisy-chain stack to be defined. When D1 is set low, no change

is made to the device address as the command is passed up the

chain. The default value of D1 is 1.

Daisy-Chain Register Readback

Bit D0 of the control register enables the readback of individual

registers from each AD7280A in a daisy chain. When Bit D0 is

set high, the application of sufficient clocks allows the data stored

in the register address identified by the read register to be shifted

out of each AD7280A in turn. This data is passed down the daisy

chain and read back by the DSP/microprocessor. When Bit D0

is set low, daisy-chain read is disabled. See the Daisy-Chain

Interface section and the Examples of Interfacing with the

AD7280A section. The default value of D0 is 1.

CELL OVERVOLTAGE REGISTER

The cell overvoltage register determines the high voltage thresh-

old of the AD7280A. Cell voltage conversions that exceed the

overvoltage threshold trigger the alert output. The AD7280A

allows the user to set the overvoltage threshold to a value from

1 V to 5 V. The resolution of the overvoltage threshold is eight

bits, that is, 16 mV. The default value of the overvoltage threshold

on power-up is 0xFF (5 V).

AD7280ABSTZ Datasheet(PDF) 29 Page - Analog Devices

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