AD7680ARMZ datasheet(6/24 Pages) AD

6 / 24 page

AD7680

Rev. A | Page 6 of 24

TIMING SPECIFICATIONS1

Table 4. VDD = 2.5 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.

Limit at TMIN, TMAX

Parameter

3 V

5 V

Unit

Description

fSCLK2

250

kHz min

2.5

MHz max

tCONVERT

20 × tSCLK

min

tQUIET

100

ns min

Minimum quiet time required between bus relinquish and start of next conversion

ns min

Minimum CS pulse width

ns min

CS to SCLK setup time

t33

ns max

Delay from CS until SDATA three-state disabled

t43

120

ns max

Data access time after SCLK falling edge

0.4 tSCLK

ns min

SCLK low pulse width

0.4 tSCLK

ns min

SCLK high pulse width

ns min

SCLK to data valid hold time

t84

ns max

SCLK falling edge to SDATA high impedance

tPOWER-UP5

μs typ

Power up time from full power-down

1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2 Mark/space ratio for the SCLK input is 40/60 to 60/40.

3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.

4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

5 See Power vs. Throughput Rate section.

200

μAI

200

μAI

1.6V

TO OUTPUT

50pF

Figure 2. Load Circuit for Digital Output Timing Specification

AD7680ARMZ Datasheet(PDF) 6 Page - Analog Devices

AD7680ARMZ Datasheet(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Descarga

Enlace URL