2XDRIVE

OUTPUT DRIVE

0

12 mA

1

25 mA

Pin #

Name

Type Description

1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127.

3

DIV2

I(PU) Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1. See table above.

4, 5

S0, S1

I(PU) Select pins for output divider determined by user. See table above.

6, 23

VDD

P

Connect to VDD.

7

ICLK

I

Reference clock input.

8

FBIN

I

Feedback clock input.

9, 20

GND

P

Connect to ground.

10

OECLK2

I(PU) CLK2 Output Enable. CLK2 tri-stated when low.

11

2XDRIVE

I(PU) Clock output drive strength doubled when high.

12-18

F0-F6

I(PU) Feedback divider word input pins determined by user. Forms a binary number from 0 to 127.

19

PDTS

I(PU) Power Down. Active low. Turns off entire chip when low. Both Clock outputs tri-stated.

21

CLK2

O

Output Clock 2. Can be the SYNC output or a low skew divide by 2 of CLK1.

22

CLK1

O

Output Clock 1.

ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

MDS 527-01 B

2

Revision 020801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com

Pin Assignment

Key:

I = Input; I(PU) = Input with internal pull-up resistor; I = Input; O = Output; P = Power supply

connection

1

8

9

2

3

4

5

6

7

10

11

12

13

14

16

15

20

17

18

19

25

24

23

22

21

26

27

28

F0

FBIN

VDD

ICLK

GND

F2

VDD

CLK1

GND

R2

R4

F6

CLK2

R3

R1

F4

F3

PDTS

R0

R5

R6

OECLK2

F1

2XDRIVE

S1

DIV2

S0

F5

S1

S0

CLK1 Output Frequency (MHz)

CLK1 Output Frequency (MHz)

pin 5

pin 4

0 to 70°

-40 to 85°

0

0

37 - 75

35 - 70

0

1

18 - 37

16 - 35

1

0

4 - 10

4 - 8

1

1

75 - 160

70 - 140

Frequency Configuration Table

Pin Description

OECLK2

DIV2

CLK2

0

X

Z

1

0

SYNC

1

1

CLK1/2

CLK2 Operation Table

Clock Drive Select Table

To cover the range from 10-18 MHz (0-70 °C) and 8-16

(-40-85°C), select address 01 to generate 2x your desired output

frequency, then configure CLK2 to generate CLK1/2