ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

MDS 527-01 B

7

Revision 020801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

ICS527R-01

0

70

°C

ICS527R-01I

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage Temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

Operating Voltage, VDD

3

3.6

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Input High Voltage, VIH, ICLK and FBIN

pins 7, 8

(VDD/2)+1

V

Input Low Voltage, VIL, ICLK and FBIN

pins 7, 8

(VDD/2)-1

V

Output High Voltage, VOH (2X DRIVE = 0)

IOH=-12mA

2.4

V

Output Low Voltage, VOL (2X DRIVE = 0)

IOL=12mA

0.4

V

Output High Voltage, VOH (2X DRIVE = 1)

IOH=-25mA

2.4

V

Output Low Voltage, VOL (2X DRIVE = 1)

IOL=25mA

0.4

V

IDD Operating Supply Current, 15 MHz IN

60MHz out, no load

8

mA

IDD Operating Supply Current, Power Down

20

µA

Short Circuit Current (2XDRIVE = 0)

CLK outputs

±70

mA

Short Circuit Current (2XDRIVE = 1)

CLK outputs

±140

mA

On-Chip Pull-up Resistor

270

k

Ω

Input Capacitance

4

pF

AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

Input Frequency, clock input

0.6

200

MHz

Output Frequency, CLK1

0 C to 70 °C

4

160

MHz

-40 C to +85 °C

4

140

MHz

CLK1 Frequency for correct SYNC operation

66

MHz

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

Output Clock Duty Cycle

at VDD/2, 15 pF load

45

50

55

%

Power Down Time,PDTS low to clocks tri-stated

50

ns

Power Up Time, PDTS high to clocks stable

10

ms

Absolute Clock Period Jitter

Deviation from mean

±90

ps

One Sigma Clock Period Jitter

40

ps

Skew of output clocks, CLK1 to CLK2

Note 1

-250

0

250

ps

Input to output skew, ICLK to FBIN

Note 1

-250

0

250

ps

Device to device skew, common ICLK

at FBIN

0

500

ps

Electrical Specifications

Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.