ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

MDS 527-01 B

1

Revision 020801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com

• Packaged as 28 pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• User determines the output frequency - no

software needed

• Slices frequency or period

• SYNC pulse output indicates aligned edges

• Input clock frequency of 600 kHz - 200 MHz

• Output clock frequencies up to 160 MHz

• Very low jitter

• Duty cycle of 45/55 up to 160 MHz

• Operating voltage of 3.3 V (±10%)

• Pin selectable double drive strength

• Multiple outputs available when combined with

Buffalo clock drivers

• Zero input to output skew

• Industrial temperature version available

• Advanced, low power CMOS process

Block Diagram

Description

Features

The ICS527-01 Clock Slicer™ is the most flexible

way to generate an output clock from an input

clock with zero skew. The user can easily configure

the device to produce nearly any output clock that

is multiplied or divided from the input clock. The

part supports non-integer multiplications and

divisions. A SYNC pulse indicates the rising clock

edges that are aligned with zero skew. Using

Phase-Locked Loop (PLL) techniques, the device

accepts an input clock up to 200 MHz and

produces an output clock up to 160 MHz.

The ICS527-01 aligns rising edges on ICLK and

FBIN at a ratio determined by the reference and

feedback dividers.

For configurable clocks that do not require

zero delay, use the ICS525.

2XDRIVE

Reference

Divide

Feedback

Divide

ICLK

FBIN

SYNC

DIV2

OECLK2

÷2

PDTS

2

S1:S0

7

R6:R0

F6:F0

7

CLK1

CLK2

1

0

PDTS

PDTS

PLL

External feedback from CLK1 or CLK2 (not both).