ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

MDS 527-01 B

3

Revision 020801

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First use DIV2 to select the function of the CLK2 output. If DIV2 is high, a divide-by-2, low skew version

of CLK1 is present on CLK2. If DIV2 is low, a SYNC pulse is generated on CLK2. The SYNC pulse goes

high synchronously with the rising edges of ICLK and CLK1 that are de-skewed. The SYNC function

operates at CLK1 frequencies up to 66 MHz. If neither CLK1/2 or a SYNC pulse are required, then CLK2

should be disabled by connecting OECLK2 to ground, which will also give the lowest jitter on CLK1.

Next, the feedback scheme should be chosen. If CLK2 is being used as a SYNC or is tri-stated, then CLK1

must be connected to FBIN. If CLK2 is selected to be CLK1 divided-by-2 (DIV2 = 1, OECLK2 = 1),

then either CLK1 or CLK2 must be connected to FBIN. The choice between CLK1 or CLK2 is illustrated

by the following example where the device has been configured to generate CLK1 that is twice the

frequency on ICLK.

ICLK

CLK1

CLK2

ICLK

CLK1

CLK2

CLK1 Feedback

CLK2 Feedback

Using CLK1 as the feedback will always result in synchronized rising edges between ICLK and CLK1. But

CLK2 could be a falling edge compared with ICLK. Therefore, wherever possible, we recommend the use

of CLK2 feedback. This will synchronize the rising edges of all 3 clocks.

More complicated feedback schemes can be used, such as incorporating multiple output buffers in the

feedback path. An example of this is given later in the datasheet. The fundamental property of the

ICS527-01 is that it aligns rising edges on ICLK and FBIN at a ratio determined by the reference and

feedback dividers.

Lastly, the divider settings should be selected. The following section describes how the dividers can be set.

The drive strength is selected by the 2XDRIVE pin. If high drive strength is not required, we recommend

tying this pin low.