Integrated

Circuit

Systems, Inc.

General Description

Features

ICS9248- 127

Block Diagram

Pentium is a trademark of Intel Corporation

I

9248-127 Rev C 8/18/00

Pin Configuration

•

Up to 124MHz frequency support.

•

Spread Spectrum for EMI control 0 to -0.5% down

spread and ±0.25% center spread

•

Serial I

Frequency Select, Spread Spectrum.

•

Provides the following system clocks

- 4-CPUs @ 3.3V, up to 124MHz.

- 13-SDRAMs @3.3V, up to 124MHz

(including SDRAM_F)

- 6-PCI (including 1 free running, PCICLK_F)

@3.3V, CPU/2 or CPU/3.

- 1-24MHz @3.3V fixed.

- 1-48MHz @3.3V fixed.

- 2-REF @3.3V, 14.318MHz.

•

Efficient Power management scheme through PCI

and STOP CLOCKS.

48-Pin SSOP

Power Groups

VDDCPU, GNDCPU = CPUCLKS, CPUCLK_F

VDDSDR, GNDSDR = SDRAMCLKS, SDRAM_F

VDDPCI, GNDPCI = PCICLKS, PCICLK_F

VDD48 = 48MHz, 24MHz

VDDREF, GNDREF = REF, X1, X2

* Internal Pull-up Resistor of 240K to VDD

The ICS9248-127 is the single chip clock solution for Desktop

designs using the VIA MVP4 and Aladdin 7 style chipset. It

provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I

Spread spectrum typically reduces system EMI by 8dB to

10dB. This simplifies EMI qualification without resorting to

board design iterations or costly shielding. The ICS9248-

127 employs a proprietary closed loop design, which tightly

controls the percentage of spreading over process and

temperature variations.

VDDREF

*PCI_STOP#/REF0

GND

X1

X2

VDDPCI

*MODE/PCICLK_F

*FS3/PCICLK0

GND

PCICLK1

PCICLK2

PCICLK3

PCICLK4

VDDPCI

BUFFER IN

GND

SDRAM11

SDRAM10

VDDSDR

SDRAM9

SDRAM8

GND

SDATA

SCLK

REF1/FS2*

VDDCPU

CPUCLK_F

CPUCLK0

GND

CPUCLK1

CPUCLK2

CLK_STOP#

GND

SDRAM_F

SDRAM0

SDRAM1

VDDSDR

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDDSDR

SDRAM6

SDRAM7

VDD48

48MHz/FS0*

24MHz/FS1*

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

CLK_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

24MHz

CPUCLK_F

CPUCLK (2:0)

SDRAM (11:0)

PCICLK (4:0)

PCICLK_F

SDRAM_F

X1

X2

BUFFER IN

XTAL

OSC

PCI

CLOCK

DIVDER

STOP

STOP

STOP

SDATA

SCLK

FS(3:0)

MODE

Control

Logic

Config.

Reg.

/ 2

REF (1:0)

LATCH

POR

2

3

12

5

4

4

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.