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ADC128S102 Datasheet(PDF) 7 Page - Texas Instruments |
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ADC128S102 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 29 page  ADC128S102 www.ti.com SNAS298G – AUGUST 2005 – REVISED JANUARY 2015 Electrical Characteristics (continued) The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX. (1) PARAMETER TEST CONDITIONS MIN TYP MAX(2) UNIT VA = VD = +2.7V to +3.6V, 0.76 1.5 mA fSAMPLE = 1 MSPS, fIN = 40 kHz Total Supply Current Normal Mode ( CS low) VA = VD = +4.75V to +5.25V, 2.13 3.1 mA fSAMPLE = 1 MSPS, fIN = 40 kHz IA + ID VA = VD = +2.7V to +3.6V, 20 nA fSCLK = 0 ksps Total Supply Current Shutdown Mode (CS high) VA = VD = +4.75V to +5.25V, 50 nA fSCLK = 0 ksps VA = VD = +3.0V 2.3 4.5 mW fSAMPLE = 1 MSPS, fIN = 40 kHz Power Consumption Normal Mode ( CS low) VA = VD = +5.0V 10.7 15.5 mW fSAMPLE = 1 MSPS, fIN = 40 kHz PC VA = VD = +3.0V 0.06 µW fSCLK = 0 ksps Power Consumption Shutdown Mode (CS high) VA = VD = +5.0V 0.25 µW fSCLK = 0 ksps AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum Clock Frequency VA = VD = +2.7V to +5.25V 8 0.8 MHz fSCLK Maximum Clock Frequency VA = VD = +2.7V to +5.25V 16 MHz 500 50 ksps Sample Rate fS VA = VD = +2.7V to +5.25V Continuous Mode 1 MSPS tCONVERT Conversion (Hold) Time VA = VD = +2.7V to +5.25V 13 SCLK cycles 40% 30 DC SCLK Duty Cycle VA = VD = +2.7V to +5.25V 70 60% tACQ Acquisition (Track) Time VA = VD = +2.7V to +5.25V 3 SCLK cycles Acquisition Time + Conversion Time Throughput Time 16 SCLK cycles VA = VD = +2.7V to +5.25V tAD Aperture Delay VA = VD = +2.7V to +5.25V 4 ns 6.6 Timing Specifications The following specifications apply for TA = 25°C, VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, and CL = 50pF. MIN and MAX apply for TA = TMIN to TMAX. PARAMETER TEST CONDITIONS MIN TYP MAX(1) UNIT tCSH CS Hold Time after SCLK Rising Edge 10 0 ns tCSS CS Setup Time prior to SCLK Rising Edge 10 4.5 ns tEN CS Falling Edge to DOUT enabled 5 30 ns tDACC DOUT Access Time after SCLK Falling Edge 17 27 ns tDHLD DOUT Hold Time after SCLK Falling Edge 4 ns tDS DIN Setup Time prior to SCLK Rising Edge 10 3 ns tDH DIN Hold Time after SCLK Rising Edge 10 3 ns 0.4 x tCH SCLK High Time ns tSCLK 0.4 x tCL SCLK Low Time ns tSCLK DOUT falling 2.4 20 ns tDIS CS Rising Edge to DOUT High-Impedance DOUT rising 0.9 20 ns (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC128S102 |
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