A25GFM080QL datasheet(17/58 Pages) AMICC

17 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new

values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) instruction must

previously have been executed. After the Write Enable

(WREN) instruction has been decoded and executed, the

device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by

driving Chip Select ( S ) Low, followed by the instruction

code and the data byte on Serial Data Input (DI).

The instruction sequence is shown in Figure 6. Only

non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1,

BP0 (bits 7, 6, 5, 4, 3, 2 of Status Register-1) and CMP,

APT, QE (bits 14, 10 and 9 of Status Register-2) can be

written. All other Status Register bits are always read as ‘0’

and will not be affected by the Write Status Register

instruction.

Chip Select ( S ) must be driven High after the eighth or

sixteenth bit of the data byte has been latched in. If not, the

Write Status Register (WRSR) instruction is not executed.

If Chip Select (

S ) is driven high after the eighth clock the

CMP and QE bits will be cleared to 0.

As soon as Chip Select ( S ) is driven High, the self-timed

Write Status Register cycle (whose duration is tW) is initiated.

While the Write Status Register cycle is in progress, the

Status Register may still be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit

is 1 during the self-timed Write Status Register cycle, and is

0 when it is completed. When the cycle is completed, the

Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the

user to change the values of the Block Protect (APT, CMP,

SEC, TB, BP2, BP1, BP0) bits, to define the size of the area

that is to be treated as read-only, as defined in Table 1. The

Write Status Register (WRSR) instruction also allows the

user to set the Status Register Protect (SRP0) bit. Those

bits are used in conjunction with the Write Protect (

W ) pin

to disable writes to the Status Register. Factory default for

all Status Register bits are 0.

Figure 6. Write Status Register (WRSR) Instruction Sequence

810

911 12 13 14 15

MSB

High Impedance

Instruction (01h)

01 2 3 4 5 6 7

16 17 18 19 20 21 22 23

Status Register In

15 14 13 12 11 10

Table 5. Protection Modes

SRP0

Status Register

Description

Software Protection

Status Register is Writable (if the WREN instruction has set the WEL

bit). The values in the CMP, APT, SRP0, SEC, TB, BP2, BP1, BP0

bits can be changed.

Hardware Protection

Status Register is hardware write protected. The values in the CMP,

APT, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be changed.

Software Protection

When

W pin is high. Status Register is Writable (if the WREN

instruction has set the WEL bit). The values in the CMP, APT,

SRP0, SEC, TB, BP2, BP1, BP0 bits can be changed.

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