A25GFM080QL datasheet(31/58 Pages) AMICC

31 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Block Erase (BE)

The Block Erase (BE) instruction sets to 1 (FFh) all bits inside

the chosen block. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded,

the device sets the Write Enable Latch (WEL).

The Block Erase (BE) instruction is entered by driving Chip

Select ( S ) Low, followed by the instruction code on Serial

Data Input (DI). Chip Select ( S ) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 20. Chip Select

( S ) must be driven High after the eighth bit of the instruction

code has been latched in, otherwise the Block Erase

instruction is not executed. As soon as Chip Select ( S ) is

driven High, the self-timed Block Erase cycle (whose duration

is tBE) is initiated. While the Block Erase cycle is in progress,

the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit

is 1 during the self-timed Block Erase cycle, and is 0 when it

is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

A Block Erase (BE) instruction applied to a page which is

protected by the Block Protect (CMP, SEC, TB, BP2, BP1,

BP0) bits (see table 1) is not executed.

Figure 20. Block Erase (BE) Instruction Sequence

Instruction (D8h or 52h)

MSB

810

0 1 234 5 6 7

24-Bit Address

28 29 30 31

22 21

3 21 00

Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.

A25GFM080QL Datasheet(PDF) 31 Page - AMIC Technology