A25GFM080QL datasheet(20/58 Pages) AMICC

20 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT)

The FAST_READ_DUAL_OUTPUT (3Bh) instruction is

similar to the FAST_READ (0Bh) instruction except the data

is output on two pins, IO0 and IO1, instead of just DO. This

allows data to be transferred from the A25LQ080 at twice the

rate of standard SPI devices.

Similar

the

FAST_READ

instruction,

the

FAST_READ_DUAL_OUTPUT instruction can operate at the

highest possible frequency of fC (See AC Characteristics).

This is accomplished by adding eight “dummy” clocks after

the 24-bit address as shown in figure 9. The dummy clocks

allow the device’s internal circuits additional time for setting

up the initial address. The input data during the dummy

clocks is “don’t care”. However, the IO0 and IO1 pins should

be high-impedance prior to the falling edge of the first data

out clock.

Figure 9. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence

Instruction (3Bh)

High Impedance

MSB

810

01 2 3 4 5 6 7

24-Bit Address

28 29 30 31

23 22 21

3 21 0

IO0

32 33 34 35 36 37 38 39

65 4

40 41 42 43 44 45 46 47

Dummy Byte

MSB

7 5 31 75 3

MSB

7 5 31 75 3 1

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Data Out 1

Data Out 2

Data Out 3

Data Out 4

DIO switches from input to output

IO1

IO0

IO1

Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.

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