PC8477B datasheet(36/54 Pages) NSC

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50 Functional Description (Continued)

TLF11332 – 13

FIGURE 5-5 Perpendicular Recording Drive RW Head and Pre-Erase Head

In 288M drives the pre-erase head leads the readwrite

head by 200 mm which translates to 38 bytes at 1 Mbs

(19 bytes at 500 kbs) For both conventional and perpen-

dicular drives WGATE is asserted with respect to the posi-

tion of the readwrite head With conventional drives this

means that WGATE is asserted when the readwrite head is

located at the beginning of the Data Field preamble With

the 288M drives since the preamble must be pre-erased

before it is rewritten WGATE should be asserted when the

pre-erase head is located at the beginning of the Data Field

preamble This means that WGATE should be asserted

when the readwrite head is at least 38 bytes (at 1 Mbs)

before the preamble See Table 4-4 for a description of the

WGATE timing for perpendicular drives at the various data

rates

Because of the 38 byte spacing between the readwrite

head and the pre-erase head at 1 Mbs the GAP2 length of

22 bytes used in the standard IBM disk format is not long

enough There is a new format standard for 288M drives at

1 Mbs called the Perpendicular Format which increases

the GAP2 length to 41 bytes (see

Figure 4-1 )

The Perpendicular Mode command of the PC8477B will put

the floppy controller into perpendicular recording mode

which allows it to read and write perpendicular media Once

this command is invoked the read write and format com-

mands can be executed in the normal manner The perpen-

dicular mode of the floppy controller will work at all data

rates adjusting the format and write data parameters ac-

cordingly See Section 428 for more details

58 DATA RATE SELECTION

The data rate can be chosen two different ways with the

PC8477B For PC compatible software the Configuration

Control Register at address 3F7 (hex) is used to program

the data rate for the floppy controller The lower bits D1 and

D0 are used in the CCR to set the data rate The other bits

should be set to zero See Table 3-6 for the data rate select

encoding

The data rate can also be set using the Data Rate Select

Again

the lower two bits of

the register are used to set the data rate The encoding of

these bits is exactly the same as those in the CCR The

remainder of the bits in the DSR are used for other func-

tions Consult the Register Description (Section 51) for

more details

The data rate is determined by the last value that is written

to either the CCR or the DSR In other words either the

CCR or the DSR can override the data rate selection of the

other register

When the data rate is selected the microengine and data

separator clocks are scaled appropriately

Also

the

DRATE0 and DRATE1 output pins will reflect the state of

the data select bits that were last written to either the CCR

or the DSR

59 WRITE PRECOMPENSATION

Write precompensation is a way of preconditioning the

WDATA output signal to adjust for the effects of bit shift on

the data as it is written to the disk surface Bit shift is caused

by the magnetic interaction of data bits as they are written

to the disk surface and has the effect of shifting these data

bits away from their nominal position in the serial MFM or

FM data pattern Data that is subject to bit shift is much

harder to read by a data separator and can cause soft read

errors Write precompensation predicts where bit shift could

occur within a data pattern It then shifts the individual data

bits early late or not at all such that when they are written

to the disk the resultant shifted data bits will be back in their

nominal position

The PC8477B supports software programmable write pre-

compensation Upon power up the default write precomp

values will be used (see Table 3-5) The programmer can

choose a different value of write precomp with the DSR

default starting track number for write precomp is track zero

This starting track number for write precomp can be

changed with the Configure command

510 LOW POWER MODE LOGIC

The PC8477B supports a low power mode in which the

oscillator and data separator circuitry are turned off The

floppy controller will typically draw about 1 mA while in low

PC8477B Datasheet(PDF) 36 Page - National Semiconductor (TI)

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