PC8477B datasheet(6/54 Pages) NSC

6 / 54 page

20 Pin Description

Symbol

PLCC

PQFP

Function

Address

These address lines from the microprocessor determine which internal FDC

cares during a DMA transfer

AVCC

Analog Supply

This pin is the 5V supply for the analog data separator

643

Chip Select

Active low input from address decoder used to enable the RD and WR inputs

during register IO Should be held inactive during DMA transfers

Data

Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB

These signals all have 12 mA buffered outputs

DACK

340

DMA Acknowledge

Active low input to acknowledge the DMA request and enable the RD

and WR inputs during a DMA transfer DACK should be held inactive high during normal read

or write accesses when CS is active When in PC-AT or Model 30 mode this signal is

enabled by bit D3 of the DOR When in PS2 mode DAK is always enabled and bit D3 of the

DOR is reserved

DENSEL

Density Select

Indicates when a high density data rate (500 kbs or 1 Mbs) or a low

density data rate (250 or 300 kbs) has been selected DENSEL is active high for high

density (525 drives) when IDENT is high and active low for high density (35 drives) when

IDENT is low DENSEL is also programmable via the Mode command (see Section 426)

DIR

Direction

This output determines the direction of the head movement (active e step in

inactive e step out) during a seek operation During read or writes DIR will be inactive

DR0

Drive Select 0 – 3

These are the decoded drive select outputs that are controlled by Digital

DR1

Output Register bits D0 D1 The Drive Select outputs are gated by DOR bits 4 – 7

DR2

DR3

DRATE0

Data Rate 01

These outputs reflect the currently selected data rate (bits 0 and 1 in the

DRATE1

CCR or the DSR whichever was written to last) These pins are totem-pole buffered outputs

(6 mA sink 4 mA source)

DRQ

DMA Request

Active high output to signal the DMA controller that a data transfer is needed

When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2

mode DRQ is always enabled and bit D3 of the DOR is reserved

DRV2

Drive2

This input indicates whether a second disk drive has been installed The state of this

pin is available from Status Register A in PS2 mode

DSKCHG

Disk Change

The input indicates if the drive door has been opened The state of this pin is

available from the Digital Input register This pin can also be configured as the RGATE data

separator diagnostic input via the Mode command (see Section 426)

GND

9 12

10 11

Ground

16 21

12 14

36 50

15 20

54 59

24 29

GNDA

Analog Ground

This is the analog ground for the data separator

PC8477B Datasheet(PDF) 6 Page - National Semiconductor (TI)

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