PC8477B datasheet(22/54 Pages) NSC

22 / 54 page

40 Command Set Description (Continued)

425 Lock Command

The Lock command allows the user full control of the FIFO

parameters after a software reset If the LOCK bit is set to 1

then the FIFO THRESH and PRETRK bits in the Configure

command are not affected by a software reset In addition

the FWR FRD and BST bits in the Mode command will be

unaffected by a software reset If the LOCK is 0 (default

after a hardware reset) then the above bits will be set to

their default values after a software reset This command is

useful if the system designer wishes to keep the FIFO en-

abled and retain the other FIFO parameter values (such as

THRESH) after a software reset

After the command byte is written the result byte must be

read before continuing to the next command The execution

of the Lock command is not performed until the result byte

is read by the mP If the part is reset after the command byte

is written but before the result byte is read then the Lock

command execution will not be performed This is done to

prevent accidental execution of the Lock command

426 Mode Command

This command is used to select the special features of the

controller The bits for the Command Phase bytes are

shown in Section 41 Command Set Summary and their

function is described below These bits are set to their de-

fault values after a hardware reset The default value of

each bit is denoted by a ‘‘bullet’’ to the left of each item The

value of each parameter after a software reset will be ex-

plained

TMR

Motor Timer mode Default after a software reset

0 e

Timers for motor on and motor off are defined for

Mode 1 (See Specify command) (default)

1 e

Timers for motor on and motor off are defined for

Mode 2 (See Specify command)

IAF

Index Address Format Default after a software reset

0 e

The controller will format tracks with the Index Ad-

dress Field included (IBM and Perpendicular for-

mat)

1 e

The controller will format tracks without including

the Index Address Field (ISO format)

IPS

Implied Seek Default after a software reset

0 e

The implied seek bit in the command byte of a

read write or scan is ignored Implied seeks could

still be enabled by the EIS bit in the Configure

command

1 e

The IPS bit in the command byte of a read write

or scan is enabled so that if it is set the controller

will perform seek and sense interrupt operations

before executing the command

LOW PWR

Low Power mode Default after a software

reset

00 e

Completely disable the low power mode (default)

01 e

Automatic low power Go into low power mode

512 ms after the head unload timer times out This

is based on 500 kbs or 1 Mbs data rate Double

this value for 250 kbs

10 e

Manual low power Go into low power mode now

11 e

Not used

ETR

Extended Track Range Default after a software reset

0 e

Track number is stored as a standard 8-bit value

compatible with the IBM ISO and Perpendicular

formats This will allow access to up to 256 tracks

during a seek operation

1 e

Track number is stored as a 12-bit value The up-

per four bits of the track value are stored in the

upper four bits of the head number in the sector

Address Field This allows access to up to 4096

tracks during a seek operation With this bit set an

extra byte is required in the Seek Command

Phase and Sense Interrupt Result Phase

FWR

FIFO Write Disable for mP write transfers to control-

ler Default after a software reset if LOCK is 0 If LOCK is 1

FWR will retain its value after a software reset

Note

This bit is only valid if the FIFO is enabled in the Configure command

If the FIFO is not enabled in the Configure command then this bit is a

don’t care

0 e

Enable FIFO Execution Phase mP write transfers

use the internal FIFO (default)

1 e

Disable FIFO All write data transfers take place

without the FIFO

FRD

FIFO Read Disable for mP read transfer from control-

ler Default after a software reset if LOCK is 0 If LOCK is 1

FRD will retain its value after a software reset

Note

This bit is only valid if the FIFO is enabled in the Configure command

If the FIFO is not enabled in the Configure command then this bit is a

don’t care

0 e

Enable FIFO Execution Phase mP read transfer

use the internal FIFO (default)

1 e

Disable FIFO All read data transfers take place

without the FIFO

BST

Burst Mode Disable Default after a software reset if

LOCK is 0 If LOCK is 1 BST will retain its value after a

software reset

Note

This bit is only valid if the FIFO is enabled in the Configure command

If the FIFO is not enabled in the Configure command then this bit is a

don’t care

0 e

Burst mode enabled for FIFO Execution Phase

data transfers (default)

1 e

Non-Burst mode enabled The DRQ or INT pin will

be strobed once for each byte to be transferred

while the FIFO is enabled

R255

Recalibrate Step Pulses The bit will determine the

maximum number of recalibrate step pulses the controller

will issue before terminating with an error Default after a

software reset

0 e

85 maximum recalibrate step pulses If ETR e 1

controller will issue 3925 recalibrate step pulses

maximum

1 e

255 maximum recalibrate step pulses If ETR e 1

controller will issue 4095 maximum recalibrate

step pulses

DENSEL

Density Select Pin Configuration This two bit val-

ue will configure the Density Select output to one of three

possible modes The default mode will configure the DEN-

SEL pin according to the state of the IDENT input pin after a

data rate has been selected That is if IDENT is high the

DENSEL pin is active high for the 500 kbs or 1 Mbs data

rates

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