TNETV1644ZDU6 datasheet(119/306 Pages) TI1

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3.7.3.5 GPIO Block Muxing

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

This block of 4 pins consists of PCI and GPIO muxed pins. The PINMUX1.PCIEN register field selects the

pin functions in the GPIO Block.

Table 3-25 summarizes the 4 pins in the GPIO Block, the multiplexed function on each pin, and the

PINMUX configurations to select the corresponding function.

Table 3-25. GPIO Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL

PCI

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

AD0/GP[0]

AD0

GP[0]

AD1/GP[1]

AD1

GP[1]

PCIEN = 1(1)

PCIEN = 0(1)

AD2/GP[2]

AD2

GP[2]

AD4/GP[3]

AD4

GP[3]

(1)

If PCIEN = 1, the internal pullup/pulldown on all GPIO Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all GPIO

Block pins are enabled.

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the

following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,

and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.

Table 3-26 provides a different view of the GPIO Block pin muxing, showing the GPIO Block function

based on PINMUX1.PCIEN setting. The selection options are also shown pictorially in Figure 3-11.

Table 3-26. GPIO Block Function Selection

PINMUX1.PCIEN

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

PCI

PCI: AD0, AD1, AD2, AD4

(Default if PCIEN = 1)

GPIO (4)

GPIO: GP[3:0]

(Default if PCIEN = 0)

The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.

Based on the PCIEN configuration pin setting, the 4 pins in the GPIO Block defaults to either PCI or GPIO

function.

In addition, the VDD3P3V_PWDN.GPIO field determines the power state of the GPIO Block pins. The

GPIO Block pins default to powered up. For more details on the VDD3P3V_PWDN.GPIO field, see

Section 3.2, Power Considerations.

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