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TNETV1644ZDU6 Datasheet(PDF) 130 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 130 Page - Texas Instruments |
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130 / 306 page  TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 3-42. EMIFA/VPSS Block Major Configuration Choices PINMUX SELECTION FIELDS (1) RESULTING PERIPHERALS/PINS MAJOR CONFIG. VPBE AND # GP PINS VPFE AND # GP PINS PCIEN AEM VENCSEL CCDCSEL PCI (2) EMIFA OPTION (FROM GP[33:5]) (FROM GP[54:34]) VENCSEL VPBE & # GP Pins CCDCSEL VPFE & # GP Pins No VENC 00 29 GP pins No CCDC 0 21 GP pins 8-bit VENC A 0 000 00, 01, 10 0, 1 - - 01 8-to-29-GP pins 16-to-24-bit VENC 8-to-16-bit CCDC 10 1 0-to-12 GP pins 0-to-12 GP pins No VENC No CCDC 8-bit EMIFA (ASYNC) 00 0 9-to-13 GP pins 11-to-19 GP pins Pinout Mode 1 with address B 0 001 (3) 00, 01 0, 1 - pins to support 32KB to 16MB 8-bit VENC (3) 8-to-16-bit CCDC (3) 01 (3) 1 (3) per CS. 0-to-4 GP pins 0-to-10 GP pins No VENC No CCDC 8-bit EMIFA (ASYNC) 00 0 17-to-21 GP pins 12 GP pins Pinout Mode 3 with address C 0 011 (3) 00, 10 0, 1 - pins to support up to 32KB per 16-bit VENC (3) 8-bit CCDC (3) 10 (3) 1 (3) CS. 0-to-4 GP pins 0-to-3 GP pins No VENC 00 22-to-26 GP pins No CCDC 0 13 GP pins 8-bit EMIFA (NAND) 8-bit VENC D 0 100 00, 01, 10 0, 1 - 01 Pinout Mode 4 12-to-17 GP pins 16-to-18-bit VENC 8-bit CCDC 10 1 2-to-9 GP pins 0-to-4 GP pins No VENC No CCDC 00 0 14-to-18 GP pins 21 GP pins 8-bit EMIFA (NAND) E 0 101 00, 01 0, 1 - Pinout Mode 5 8- bit VENC 8-to-16-bit CCDC 01 1 4-to-9 GP pins 0-to-12 GP pins No VENC 00 29 GP pins No CCDC 0 13 GP pins 8-bit VENC F 1 000 00, 01, 10 0, 1 PCI - 01 8-to-29 GP pins 16-to-24-bit VENC 8-bit CCDC 10 1 0-to-12 GP pins 0-to-4 GP pins No VENC No CCDC 00 0 14-to-18 GP pins 13 GP pins 8-bit EMIFA (NAND) G 1 101 00, 01 0, 1 PCI Pinout Mode 5 8-bit VENC 8-bit CCDC 01 1 4-to-9 GP pins 0-to-4 GP pins (1) For additional pin mux details for each Sub-Block, see Table 3-43 through Table 3-49, EMIFA/VPSS Sub-Block 0 Configuration Choices, and Table 3-50 through Table 3-54, EMIFA/VPSS Sub-Block 1 Configuration Choices. (2) PCI pins span across multiple Pin Mux Blocks (Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks). This table only refers to the PCI pins in the EMIFA/VPSS Block. (3) If PINMUX0.AEM = 001 or 011, it is not possible to get LCD_FIELD pin for VPBE, nor C_WE pin for VPFE. 130 Device Configurations Submit Documentation Feedback |
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