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TNETV1644ZDU6 Datasheet(PDF) 133 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 133 Page - Texas Instruments |
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133 / 306 page  TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 3-44. EMIFA/VPSS Sub-Block 0 Configuration Choice B(1) MAJOR MINOR PINMUX SELECTION FIELDS RESULTING PERIPHERALS/PINS CONFIG CONFIG PCIEN AEM AEAW OTHERS PCI EMIFA VPFE # GPIO PINS OPTION OPTION 8-bit EMIFA (Async) Pinout Config Summary No PCI No CCDC 11 GP pins mode 1 w/ EM_A[21:0] 0 = GP[54, CCDCSEL = 0 - 43:36] HVDSEL = 0 - 0 = GP[53:52] CWENSEL = 0 0 = EM_R/W - B B1 0 001 100 CFLDSEL = 0 0 = EM_A21 - 0 = CI10SEL = 0 - - - EM_A[19:20] 0 = CI32SEL = 0 - EM_A[17:18] 0 = CI54SEL = 0 - EM_A[15:16] 0 = CI76SEL = 0 - EM_A[13:14] 8-bit EMIFA (Async) Pinout 8-to-16-bit 0-to-10 GP Config Summary No PCI mode 1 w/ CCDC pins EM_A[12:0] only 1 = PCLK, CCDCSEL = 1 - - YI[7:0] HVDSEL = 0,1 - 1 = VD, HD 0 = GP[53:52] B B2 0 001 000 CWENSEL = 0 0 = EM_R/W - - 0 = EM_A21 CFLDSEL = 0,1 1 = C_FIELD - - (not used) CI10SEL = 0,1 - 1 = CI[1:0] 0 = GP[45:44] CI32SEL = 0,1 - 1 = CI[3:2] 0 = GP[47:46] CI54SEL = 0,1 - 1 = CI[5:4] 0 = GP[49:48] CI76SEL = 0,1 - 1 = CI[7:6] 0 = GP[51:50] 8-bit EMIFA (Async) Pinout 8-to-14-bit Config Summary No PCI mode 1 w/ 0-to-8 GP pins CCDC EM_A[14:0] only 1 = PCLK, CCDCSEL = 1 - - YI[7:0] HVDSEL = 0,1 - 1 = VD, HD 0 = GP[53:52] B B3 0 001 001 CWENSEL = 0 0 = EM_R/W - - 0 = EM_A21 CFLDSEL = 0,1 1 = C_FIELD - (not used) - CI10SEL = 0,1 - 1 = CI[1:0] 0 = GP[45:44] CI32SEL = 0,1 - 1 = CI[3:2] 0 = GP[47:46] CI54SEL = 0,1 - 1 = CI[5:4] 0 = GP[49:48] 0 = CI76SEL = 0 - - EM_A[13:14] (1) Italics indicate mandatory settings for a given Minor Configuration option. Submit Documentation Feedback Device Configurations 133 |
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