TNETV2501INPGF datasheet(35/197 Pages) TI1

35 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

UART Pins

UART transmit data output. The UART.TX signal outputs a value of 1 during and after

reset.

UART receive data input

I2C Pins

SCL

I/O/Z

C, F, M

I2C clock bidirectional port. (Open collector I/O)

SDA

I/O/Z

C, F, M

I2C data bidirectional port. (Open collector I/O)

Timer Pins

TIM0

I/O/Z

F, G, H,

Input/Output pin for Timer 0. The TIM0 pin can be configured as an output or an input

via the Timer Signal Selection Register (TSSR).When configured as an output, the TIM0

pin can signal a pulse or a change of state when the Timer 0 count matches its period.

When configured as an input, the TIM0 pin can be used to provide the clock source for

Timer 0 (external clock source mode) or it can be used to start/stop the timer from

counting (clock gating mode). This pin can also be used as general-purpose I/O. The

TIM0 pin is configured as an input after reset.

TIM1

I/O/Z

F, G, H,

Input/Output pin for Timer 1. The TIM1 pin can be configured as an output or an input

via the Timer Signal Selection Register (TSSR).When configured as an output, the TIM1

pin can signal a pulse or a change of state when the Timer 1 count matches its period.

When configured as an input, the TIM1 pin can be used to provide the clock source for

Timer 1 (external clock source mode) or it can be used to start/stop the timer from

counting (clock gating mode). This pin can also be used as general-purpose I/O. The

TIM1 pin is configured as an input after reset.

Supply Pins

VSS

Digital Ground. Dedicated ground for the device.

CVDD

Digital Power, + VDD. Dedicated power supply for the core CPU.

PVDD

Digital Power, + VDD. Dedicated power supply for the PLL module.

No Connect

DVDD

Digital Power, + VDD. Dedicated power supply for the I/O pins.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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