TNETV2501INPGF datasheet(67/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

Table 3−12. PLL Control/Status Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15:7

000000000

Reserved. Reads return 0. Writes have no effect.

STABLE

Oscillator output stable. This bit indicates if the OSCOUT output has

stabilized.

STABLE = 0:

Oscillator output is not yet stable.

Oscillator counter is not done counting

41,032 reference clock cycles.

STABLE = 1:

Oscillator output is stable. This is true if

any one of the three cases is true:

a) Oscillator counter has finished counting.

b) Oscillator counter is disabled.

c) Test mode.

LOCK

Lock mode indicator. This bit indicates whether the clock generator

is in its lock mode.

LOCK = 0:

The PLL is in the process of getting a phase

lock.

LOCK = 1:

The clock generator is in the lock mode. The

PLL has a phase lock and the output clock of

the PLL has the frequency determined by the

PLLM register and PLLDIV0 register.

Reserved

Reserved. Reads return 0. Writes have no effect.

PLLRST

R/W

Asserts RESET to PLL

PLLRST = 0:

PLL reset released

PLLRST = 1:

PLL reset asserted

OSCPWRDN

R/W

Sets internal oscillator to power-down mode

OSCPWRDN = 0:

Oscillator operational

OSCPWRDN = 1:

Oscillator set to power-down mode based on

state of CLKMD0 bit of Clock Mode Control

When CLKMD0 = 0, the internal oscillator is set

to power-down mode when the clock generator

is set to its idle mode [CLKIS bit of the IDLE

Status Register (ISTR) becomes 1].

When CLKMD0 = 1, the internal oscillator is set

to power-down mode immediately after the

OSCPWRDN bit is set to 1.

PLLPWRDN

R/W

Selects PLL power down

PLLPWRDN = 0:

PLL operational

PLLPWRDN = 1:

PLL placed in power-down state

PLLEN

R/W

PLL mode enable. This bit controls the multiplexer before dividers

D1, D2, and D3.

PLLEN = 0:

Bypass mode. Divider D1 and PLL are

bypassed. SYSCLK1 to 3 divided down

directly from input reference clock.

PLLEN = 1:

PLL mode. Divider D1 and PLL are not

bypassed. SYSCLK1 to 3 divided down from

PLL output.

TNETV2501INPGF Datasheet(PDF) 67 Page - Texas Instruments

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