AT89C51ED2-RDTIM datasheet(59/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Table 42. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

Reset Value = XXX0 0000b

Not bit addressable

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4BRR

Baud Rate Run Control bit

Cleared to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

3TBCK

Transmission Baud rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

2RBCK

Reception Baud Rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

SPD

Baud Rate Speed Control bit for UART

Cleared to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

0SRC

Baud Rate Source select bit in Mode 0 for UART

Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2

mode).

Set to select the internal Baud Rate Generator for UARTs in mode 0.

AT89C51ED2-RDTIM Datasheet(PDF) 59 Page - ATMEL Corporation

AT89C51ED2-RDTIM Datasheet(HTML) 59 Page - ATMEL Corporation

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