GPL32611B datasheet(13/22 Pages) GENERALPLUS

13 / 22 page

GPL32611B

Proprietary & Confidential

Oct. 02, 2018

Version: 1.3

5.12.2. Key scan function

The Key Scan function is output at IOA[7:0] and input with

IOA[15:8] under 64 keys mode.

Additional three outputs IOB[2:0]

are required under 88 keys mode.

The IOA [7:0] are shared with

LCD data [7:0], which means the Key Scan function can still work

even when 8-bit-data-bus LCD Display is turned on.

However,

when 16-bit data bus TFT-LCD panel is connected, the Key Scan

function cannot work.

Note that when Key Scan function IOA is

shared with LCD panel, each output must connect a diode serially

to the key pad, which prevents possible LCD glitch caused by

contention when more than one key is pressed at the same time.

The following diagram shows an example of the connection.

IOA[0]

IOA[1] IOA[2] IOA[3] IOA[4] IOA[5] IOA[6] IOA[7]

IOA[8]

IOA[9]

IOA[10]

IOA[11]

IOA[12]

IOA[13]

IOA[14]

IOA[15]

CLD[0] CLD[1] CLD[2] CLD[3] CLD[4] CLD[5] CLD[6] CLD[7]

5.13. Timer / Counter

Six 16-bit timers/counters are designed in GPL32611B: TimerA,

TimerB, TimerC, TimerD, TimerE, and TimerF.

The clock source

of each timer can be set individually.

For TimerA to TimerD, an

INT will be sent to CPU when timer overflow occurs.

Besides,

Capture, Comparison and PWM functions are also provided by

TimerA/TimerB/TimerC.

Clock Source A

Clock Source B

Fosc/2

2048Hz

Fosc/256

1024Hz

32768Hz

256Hz

8192Hz

Time Base B

4096Hz

Time Base A

Another Timer

INT1

INT2

The GPL32611B also features a Time Base controller to generate

slow and precise interrupts form 32768Hz crystal.

The following

table shows the available Time Base.

TimeBase A

TimeBase B

TimeBase C

8Hz

128Hz

1Hz

16Hz

256Hz

2Hz

32Hz

512Hz

4Hz

64Hz

1024Hz

5.14. Watchdog

The purpose of watchdog is to monitor whether or not the system

is operating normally.

Within a certain period, watchdog must be

cleared; otherwise, CPU assumes the program has been running

in an abnormal condition.

As a result, the CPU will reset the

system to the initial state and start running the program all over

again.

In GPL32611B, the clear period is software programmable.

If watchdog is cleared before the period expires, the system will

not be reset.

5.15. Serial Interface

5.15.1. Serial Peripheral Interface (SPI)

The SPI interface is a master/slave interface that enables

synchronous serial communication with slave/master peripherals.

Two 8-byte FIFOs are used for transmitting and receiving

functions.

Four types of timings are supported and shown in the

following diagram.

MSB

LSB

SCLK

SFRM

SSPTXD

SSPOE

8 bits

MSB

LSB

SSPRXD

SPO = 0, SPH = 0, only this mode is supported in SPI slave mode.

MSB

LSB

SCLK

SFRM

SSPTXD

SSPOE

8 bits

MSB

LSB

SSPRXD

SPO = 0, SPH = 1

GPL32611B Datasheet(PDF) 13 Page - Generalplus Technology Inc.

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