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GPL32611B Datasheet(PDF) 5 Page - Generalplus Technology Inc. |
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GPL32611B Datasheet(HTML) 5 Page - Generalplus Technology Inc. |
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5 / 22 page ![]() GPL32611B © Generalplus Technology Inc. Proprietary & Confidential 5 Oct. 02, 2018 Version: 1.3 Low voltage reset. 1 data lane MIPI Real-time clock (RTC) with independent power supply. 96MHz, 27MHz and 12MHz PLL. 16-bit stereo DAC (2-channel) for audio playback. 12-bit ADC with 6 line-in channels. MIC with PGAC. (program gain control) TV encoder supporting NTSC/PAL and de-flicker and scalar function. 3. BLOCK DIAGRAM AHB for memory I/F AHB to APB Bridge NAND flash / xD APB Cache = 8KB Boot ROM = 24KB LDM =38KB DMA Controller 4 channels ARM7TDMI With Embeded ICE Memory / SDRAM Controller MP3 GPIO Interrupt Controller Key scan RTC Timebase 6 Timers UART System control BCH SD/MMC X2 SPI X2 MS/MS pro ADC USB2.0 host/device DAC MIC PPU JPEG/ MPEG4 TV Encoder De- flicker SPU CSI TFT STN MIPI FD Built-in SDRAM 128Mb Regulator (3.3V to 1.2V) |
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