XRT83SL34 datasheet(12/80 Pages) EXAR

12 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

µPTS1

µPTS2

RCLKE

TCLKE

106

107

106

107

Microprocessor Type Select Input Pins - Host Mode:

Microprocessor Type Select Input Bit 1

Microprocessor Type Select Input Bit 2

Receive Clock Edge select - Hardware mode

See “Receive Clock Edge - Hardware Mode” on page 5.

Transmit Clock Edge select - Hardware mode

See “Transmit Clock Edge - Hardware Mode” on page 6.

NOTE: These pins are internally pulled “Low” with a 50k

Ω resistor.

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]/

D[1]/

D[0]/

LOOP1_0

LOOP0_0

LOOP1_1

LOOP0_1

LOOP1_2

LOOP0_2

LOOP1_3

LOOP0_3

I/O

Microprocessor Read/Write Data Bus Pins - Host Mode

Data Bus[7]

Data Bus[6]

Data Bus[5]

Data Bus[4]

Data Bus[3]

Data Bus[2]

Data Bus[1]

Data Bus[0]

Loop-back Control pin, Bits [1:0]_Channel_n - Hardware Mode

Pins 42 - 49 control which Loop-Back mode is selected per channel. See

“Loop-Back Control Pins - Hardware Mode:” on page 14.

NOTE: Internally pulled “Low” with a 50k

Ω resistor.

µPCLK

ATAOS

Microprocessor Clock Input - Host Mode

Input clock for synchronous microprocessor operation. Maximum clock rate

is 54 MHz.

NOTE: This pin is internally pulled “Low” for asynchronous microprocessor

interface when no clock is present.

Automatic Transmit "All Ones” - Hardware mode

This pin functions as an Automatic Transmit “All Ones”. See “Automatic

Transmit “All Ones” Pattern - Hardware Mode” on page 13.

SIGNAL NAME

PIN #TYPE

DESCRIPTION

µPTS2

µPTS1

µP Type

68H C 11, 8051, 80C 188 (a syn c.)

M o to ro la 6 8 K (a syn c.)

In te l x8 6 (syn c.)

M o to ro la 860 (syn c.)

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